AMD did some news last night at Keynote ComputerEx 2021 when AMD CEO Dr. Lisa Su showed the company’s new 3D Tiplet technology developed in partnership with TSMC.
The long and short of these is that, rather than spreading on a wider mur, components of the CPU as the logical unit and the cache are stacked on each other, using a vertical space rather than to develop the total surface of the chip in a flat wafer.
Although the technology is mainly pioneering by TSMC, AMD seems to be the first chipmaker to take advantage of the new process by introducing new “vertical cache” to its Ryzen series processors.
Without moving too much in the architecture of the computer system, the cache memory is the part of the processor that stores the most relevant data instructions and programs of the processor at any time. The bigger the cache, the more it is possible to store data so that the processor is not necessary to retrieve new RAM data, which takes longer and slows out performance.
According to SU, stacking a 64 MB SRAM node on the CCD (the part of the processor containing a collection of processing cores), AMD can triple the cache L3 available on a 16-core processor of up to 64 MB to 192. Mo.
This change alone has given the AMD prototypes, a Ryzen 9 5900x processor using the new 3D V-Cache cache cache technology, an increase of 12% of 12% during a demonstration of war equipment 5. This type of performance increase is typically what you see between processor generations, thus increase the performance of an existing 12% processor using a single 3D chiplet design is quite impressive.
And while this technology has not yet been engaged in a consumer processor, AMD indicates that it “is in the process of starting production on future high-end IT products with 3D chiplettes by the end of this year”.
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Without becoming too deeply in the weeds of Moore’s law, writing has been on the wall of the assumption that our computers would become gradually faster for more than ten years. We can no longer rely on the genius of the raw force of smaller and smaller transistors to make our computers more and more powerful. We are approaching the literal physical limit of how these transistors can be before individual silicon atoms begin to become unreliable mediums for electric current.